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IRDC3897-P1V2 12/8/2011 1 user guide for ir3897 evaluation board 1.2vout description the ir3897 is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 4mm x 5 mm power qfn package. key features offered by the ir3897 include internal digital soft start/soft stop, precision 0.5vreference voltage, power good , thermal protection, programmable switching frequency, enable input, input under-voltage lockout for proper start-up, enhanced line/ load regulation with feed forward, external frequency synchronization with smooth clocking, internal ldo and pre-bias start- up. output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous mosfet for optimum cost and performance and the current limit is thermally compensated. this user guide contains the schematic and bill of materials for the ir3897 evaluation board. the guide describes operation and use of the evaluation board itself. detailed application information for ir3897 is available in the ir3897 data sheet. board features ? v in = +12v (+ 13.2v max) ?v out = +1.2v @ 0- 4a ? f s =600khz ? l= 1.5uh ? c in = 2x10uf (ceramic 1206) + 1x330uf (electrolytic) ? c out =4x22uf (ceramic 0805) sup ir buck tm
IRDC3897-P1V2 12/8/2011 2 a well regulated +12v input supply should be connected to vin+ and vin-. a maximum of 4a load should be connected to vout+ and vout-. the inputs and output connections of the board are listed in table i. ir3897 has only one input supply and internal ldo generates vcc from vin. if operation with external vcc is required, then r15 can be removed and external vcc can be applied between vcc+ and vcc- pins. vin pin and vcc/ldo_out pins should be shorted together for external vcc operation. the output can track voltage at the vp pin. for this purpose, vref pin is to be connected to ground (use zero ohm resistor for r21). the value of r14 and r20 can be selected to provide the desired tracking ratio between output voltage and the tracking input. connections and operating instructions layout the pcb is a 4-layer board (2.23?x2?) using fr4 material. all layers use 2 oz. copper. the pcb thickness is 0.062?. the ir3897 and other major power components are mounted on the top side of the board. power supply decoupling capacitors, the bootstrap capacitor and feedback components are located close to ir3897. the feedback resistors are connected to the output at the point of regulation and are located close to the supirbuck ic. to improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. table i. connections connection signal name vin+ vin (+12v) vin- ground of vin vout+ vout(+1.2v) vout- ground for vout vcc+ vcc/ ldo_out pin vcc- ground for vcc input enable enable pgood power good signal agnd analog ground
IRDC3897-P1V2 12/8/2011 3 connection diagram vin gnd gnd vout enable vddq vref sync s-ctrl agnd pgood vsns vcc+ vcc- top view bottom view fig. 1: connection diagram of ir3899/98/97 evaluation boards
IRDC3897-P1V2 12/8/2011 4 fig. 2: board layout-top layer fig. 3: board layout-bottom layer single point connection between agnd and pgnd
IRDC3897-P1V2 12/8/2011 5 fig. 5: board layout-mid layer 2 fig. 4: board layout-mid layer 1
IRDC3897-P1V2 12/8/2011 6 fig. 6: schematic of the ir3897 evaluation board
IRDC3897-P1V2 12/8/2011 7 bill of materials item qty part reference value description manufacturer part number 1 1 c1 330uf smd electrolytic f size 25v 20% panasonic eev-fk1e331p 2 2 c4 c5 10uf 1206, 25v, x5r, 20% tdk c3216x5r1e106m 3 4 c7 c12 c14 c24 0.1uf 0603, 25v, x7r, 10% murata grm188r71e104k a01b 4 1 c8 2200pf 0603,50v,x7r murata grm188r71h222k a01b 5 1 c11 120pf 0603, 50v, np0, 5% murata grm1885c1h121j a01d 6 4 c15 c16 c17 c18 22uf 0805, 6.3v, x5r, 20% tdk c2012x5r0j226m 7 1 c23 2.2uf 0603, 16v, x5r, 20% tdk c1608x5r1c225m 8 1 c26 10nf 0603, 25v, x7r, 10% murata grm188r71e103k a01j 9 1 c32 1.0uf 0603, 25v, x5r, 10% murata grm188r61e105k a12d 10 1 l1 1.5uh smd 7.05x6.6x4.8mm,6.7m ? cyntec pcmb065t-1r5ms 11 1 r1 3.01k thick film, 0603,1/10w,1% panasonic erj-3ekf3011v 12 2 r2 r11 3.32k thick film, 0603,1/10w,1% panasonic erj-3ekf3321v 13 2 r3 r12 2.37k thick film, 0603,1/10w,1% panasonic erj-3ekf2371v 14 1 r4 100 thick film, 0603,1/10w,1% panasonic erj-3ekf1000v 15 1 r6 20 thick film, 0603,1/10w,1% panasonic erj-3ekf20r0v 16 1 r9 39.2k thick film, 0603,1/10w,1% panasonic erj-3ekf3922v 17 5 r10 r13 r14 r15 r50 0 thick film, 0603,1/10w panasonic erj-3gey0r00v 18 2 r17 r18 49.9k thick film, 0603,1/10w,1% panasonic erj-3ekf4992v 19 1 r19 7.5k thick film, 0603,1/10w,1% panasonic erj-3ekf7501v 20 1 u1 ir3897 pqfn 4x5mm ir ir3897mpbf
IRDC3897-P1V2 12/8/2011 8 typical operating waveforms vin=12.0v, vo=1.2v, io=0-4a, room temperature, no airflow fig. 10: output voltage ripple, 4a load ch 2 : v out , fig. 11: inductor node at 4a load ch 2 :lx fig. 8: start up at 4a load, ch 1 :v in , ch 2 :v o , ch 3 :vcc, ch 4 :p good fig. 7: start up at 4a load ch 1 :v in , ch 2 :v o , ch 3 :p good ch 4 :enable fig. 9: start up with 1v pre bias , 0a load, ch 2 :v o fig. 12: short circuit (hiccup) recovery ch 2 :v out , ch4:iout
IRDC3897-P1V2 12/8/2011 9 typical operating waveforms vin=12.0v, vo=1.2v, io=0-4a, room temperature, no air flow fig. 13: transient response, 2.0a to 4a step ch 2 :v out ch4-iout
IRDC3897-P1V2 12/8/2011 10 typical operating waveforms vin=12.0v, vo=1.2v, io=0-4a, room temperature, no air flow fig. 14: bode plot at 4a load shows a bandwidth of 112.6khz and phase margin of 52.4 degrees
IRDC3897-P1V2 12/8/2011 11 typical operating waveforms vin=12.0v, vo=1.2v, io=0-4a, room temperature, no air flow fig (16) feed forward for vin change from 7 to 16v and back to 7v ch 2 -vout ch 4 -vin fig (15) soft start and so ft stop using s_ctrl pin
IRDC3897-P1V2 12/8/2011 12 fig.18: power loss versus load current fig.17: efficiency versus load current typical operating waveforms vin=12.0v, vo=1.2v, io=0-4a, room temperature, no air flow 70 72 74 76 78 80 82 84 86 88 90 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 load current (a) efficiency (%) 0.100 0.175 0.250 0.325 0.400 0.475 0.550 0.625 0.700 0.775 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 load current (a) power dissipation(w)
IRDC3897-P1V2 12/8/2011 13 thermal images vin=12.0v, vo=1.2v, io=0-4a, room temperature, no air flow fig. 19: thermal image of the board at 4a load test point 1 is ir3897 test point 2 is inductor
IRDC3897-P1V2 12/8/2011 14 pcb metal and component placement evaluations have shown that the bes t overall performance is achieved using the substrate/pcb layout as shown in following figures. pqfn devices shoul d be placed to an accuracy of 0.050mm on both x and y axes. self-centering behavior is highly depend ent on solders and proce sses, and experiments should be run to confirm the limits of self-centering on specific proce sses. for further information, please refer to ?supirbuck? multi-chip module (mcm) power quad flat no-lead (pqfn) board mounting application note .? (an1132) figure 20: pcb metal pad spacing (all dimensions in mm)
IRDC3897-P1V2 12/8/2011 15 solder resist ir recommends that the lar ger power or land area pads are solder mask defined (smd.) this allows the underlying copper trac es to be as large as possible, which helps in terms of current carrying capability and device cooling capability. when using smd pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the solder mask window, in order to accommodate any layer to la yer misalignment. (i.e . 0.1mm in x & y.) however, for the smaller signal type leads ar ound the edge of the devic e, ir recommends that these are non solder mask defined or copper defined. when using nsmd pads, the solder resist window should be larger than the copper pad by at least 0.025mm on each edge, (i.e. 0.05mm in x&y,) in order to accommodate any layer to layer misalignment. ensure that t he solder resist in-between t he smaller signal lead areas are at least 0.15mm wide, due to the high x/y as pect ratio of the solder mask strip. figure 21: solder resist
IRDC3897-P1V2 12/8/2011 16 stencil design figure 22: stencil pad spacing (all dimensions in mm) stencils for pqfn can be used with th icknesses of 0.100-0.250mm (0.004-0. 010"). stencils thinner than 0.100mm are unsuitable because they depos it insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. evaluatio ns have shown that the best overall performance is achieved using the stencil design s hown in following figure. this design is for a stencil thickness of 0.127mm (0.005").the reduction s hould be adjusted for stencils of other thicknesses.
IRDC3897-P1V2 12/8/2011 17 ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 this product has been designed a nd qualified for the industrial market visit us at www.irf.com for sales contact information data and specifications subject to change without notice.12/11 package information figure 23: package dimensions

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